Design Verification Engineer

Overview

As a Design Verification Engineer, you help ensure robust digital verification for mixed-signal IC developments. You will work within a multidisciplinary Verifications team to develop advanced verification environments and refine verification methodologies. You contribute to challenging, cutting-edge projects for global consumer brands within a growing semiconductor group. You will collaborate cross-functionally, influence verification practices, and support organizational growth and development. This role offers a hybrid Edinburgh-based setup with opportunities for career progression and meaningful impact in verification strategy and execution.

Pay / Benefits

• strong benefits package
• personal and professional development
• RSUs
• flat culture
• competitive compensation
• relocation support

Responsibilities

• Plan and execute verification activities for digital and mixed-signal ICs
• Develop and maintain verification environments and testbenches (e.g., UVM)
• Analyze functional and code coverage; drive coverage goals
• Debug complex verification issues and drive improvements in methodologies
• Mentor junior engineers and lead verification activities on larger projects

Key requirements

• Metric-driven verification
• Verification planning
• Directed and constrained-random verification
• Functional and code coverage analysis
• Strong SystemVerilog and SystemVerilog Assertions (SVA)
• Testbench development using UVM
• Strong debugging skills
• TCL or Perl scripting
• Power-aware verification using CPF/UPF
• Formal verification and qualification techniques (nice to have)

• Mentoring capability
• Problem-solving mindset
• Cross-functional collaboration
• SystemVerilog
• SystemVerilog Assertions (SVA)
• UVM

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