Senior FPGA/ASIC Design Engineer — RTL & System Validation

AMD in Edinburgh seeks a senior FPGA/ASIC engineer to design, integrate, and validate high‑performance RTL for advanced IPs and subsystems across FPGA and ASIC platforms.

You will lead technical discussions, mentor junior engineers, and help shape best practices, collaborating with global teams on challenging hardware and software integration.

This role offers hands‑on ownership, visibility, and clear opportunities for career growth within a world‑class innovation environment.

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