Director - Hardware Engineering, AI Infrastructure Systems

About Us

Axelera AI is not your regular deep-tech company. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us.

In just five years, we have raised a total of $450 million and have built a world-class team of 250+ employees (including 60+ PhDs with more than 40,000 citations), both remotely from 20 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands.

We have also launched our Metis™ AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million.

Our unwavering commitment to innovation has firmly established us as a global industry pioneer.

Are you up for the challenge?

Position Overview

We are looking for an entrepreneurial, technically exceptional engineering leader to establish and run Axelera’s AI Infrastructure Systems division within the AI Integrated Systems (AIS) group. This is a new function, created to realize and deliver our next-generation accelerator silicon into datacenter-class form factors from PCIe accelerator cards and OAM-class modules to full 1U/2U rack systems and dense compute nodes targeting enterprise AI, sovereign cloud and HPC customers.

You will build the team, shape the technical roadmap, and own end-to-end delivery of board- and system-level products for two strategic programmes. You will partner closely with the engineering leadership of the Embedded AI product line within AIS, System and Platform Architecture within R&D, the silicon organisation, the Voyager SDK/software group, and Axelera’s go-to-market teams serving hyperscalers, sovereign AI initiatives and the European HPC ecosystem.

This role is deeply hands-on, owning implementation, validation, and delivery of platform systems. You will review schematics and layouts, challenge power and thermal budgets, shape the BMC and platform-firmware stack, and walk the lab floor during bring-up. Strategic leadership without technical depth will not work here.

Key responsibilities:

• Build the Infrastructure Systems engineering team from the ground up: hire, structure and mentor a multidisciplinary organisation covering hardware architecture, PCB design, power/thermal/mechanical engineering, firmware and platform validation with in-house and 3rd-party resources
• Define the technical roadmap for the division’s board- and system-level server products—PCIe Gen6/CXL accelerator cards, OAM modules and UBB baseboards, and full 1U/2U rack systems, evolving toward rack-scale solutions including networking fabric and storage architecture—aligned with the next-generation system and silicon roadmap.
• Serve as the technical authority across system implementation, including schematics, PCB stack-ups, high-speed signaling (PCIe Gen5/6, CXL, high-speed SerDes), enterprise memory, power delivery and VRM design, SI/PI methodology, and mechanical/thermal integration.
• Own end-to-end execution from concept through design reviews, bring-up, validation, reliability qualification, DFM/DFT/DFR and mass-production readiness, including NPI and ramp with tier-1 CMs and ODMs. Make the build-vs-partner call on each program leading designs in-house where it differentiates, and co-designing with ODM partners where time-to-market or scale demands it.
• Drive datacenter-grade platform engineering: BMC-based management, Redfish/IPMI, UEFI/BIOS firmware, secure boot and root-of-trust, platform firmware resilience, enterprise RAS features, and out-of-band telemetry.
• Lead the thermal and mechanical strategy for high-power accelerator platforms, including air-cooled rack designs and, where appropriate, direct liquid cooling (DLC) and immersion-ready variants.
• Partner with the Embedded AI engineering leadership within AIS to align board and system-level execution across the two product lines, sharing reference designs, validation assets and CM/ODM relationships wherever it accelerates both streams.
• Collaborate with Platform Architecture, product management, silicon, SDK and software teams to refine and realize platform requirements (e.g. memory topology, interconnect, power states, telemetry) so that the server products showcase the accelerator’s capabilities at rack and cluster scale.
• Engage directly with strategic customers, system integrators and ecosystem partners (hyperscalers, sovereign cloud operators, HPC centres, OEMs/ODMs) to shape requirements and win design-ins.
• Define and enforce engineering processes, documentation standards, validation methodologies and quality gates for the new division, mapped to Axelera’s NPD framework.
• Identify and mitigate technical risks, resolve engineering escalations, and drive debugging and root-cause analysis during development, qualification and early production.
• Own the division’s …

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