Senior IC Layout Engineer (Hybrid) – High-Speed Analog IP

IC Resources in Cambridge is seeking a Senior IC Layout Engineer to own the custom layout and verification of analog circuits, blocks, and IP for multi-Gigabit SerDes and memory IO. The role offers hybrid working with 3 days in the office.

You will lead chip layout activities and benefit from opportunities for career progression, with experience in high-speed designs valued. Tools include Cadence Virtuoso, Spectre/HSpice and Calibre across advanced nodes.

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