Cadence Design Systems in Edinburgh, UK, seeks a Principal Digital Design Engineer to drive high-performance RTL development for advanced SoCs within the PSG. You will own RTL from architectural concepts through synthesis and handoff, collaborating with architecture, verification, and physical design teams to solve complex silicon problems.
The role targets senior engineers with expertise in SystemVerilog, RTL debugging, and timing closure, contributing to cutting-edge semiconductor solutions
#J-18808-Ljbffr
Full job description from WhatJobs. Apply for this role →
City of Edinburgh
Cadence Design Systems in Edinburgh, UK, seeks a Principal Digital Design Engineer to drive high-performance RTL development for advanced SoCs…
City of Edinburgh
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cambridge
I’m working with one of the UK’s most exciting semiconductor companies, currently hiring Silicon Verification Engineers to join its AI compute team…
West of England
As a ASIC RTL Design Engineer at Nordic Semiconductor, you will play an important role in developing the next generation of cutting-edge Wi-Fi SoCs…
Cambridgeshire and Peterborough
I'm working with one of the UK's most exciting semiconductor companies, currently hiring Silicon Verification Engineers to join its AI compute team…
City of Edinburgh
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Explore: Engineering recruitment Specialist jobs in Edinburgh
Worked with Verifera as a candidate or employer? Your honest review helps the next person trust verified hiring.