Swedium Global Services is the growing System Engineering and Solution Company, offers services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy and Outsourcing services to our clients across the globe for an onsite and offshore business model. Swedium Global is having presence in Sweden, Finland, Poland, Czech Republic and in India.
Location - Remote from UK/EU
Job Title - Senior Physical Design Engineer
We are looking forPhysical Design (PD) and Static Timing Analysis (STA) Engineers .
Key Responsibilities
- Perform Static Timing Analysis (STA) for advanced-node ASIC/SoC designs.
- Drive timing closure across multiple design stages and operating corners.
- Analyze and resolve setup and hold timing violations.
- Perform timing analysis across multiple PVT (Process, Voltage, Temperature) corners and modes.
- Work closely with Physical Design, RTL, Synthesis, and Signoff teams to identify and resolve timing issues.
- Perform timing path analysis and recommend optimization strategies.
- Review and debug timing constraints, including SDC constraints.
- Support timing signoff activities for advanced technology nodes.
- Analyze and resolve issues related to clock skew, transition, capacitance, and fanout.
- Collaborate with cross-functional teams to achieve timing, power, and area targets.
- Support design implementation and signoff activities for TSMC advanced process technologies (<5nm) .
- Participate in methodology development and automation to improve timing analysis and closure efficiency.
Required Skills
- 5+ years of relevant experience in Physical Design / STA.
- Strong hands-on experience in Static Timing Analysis and timing closure .
- Experience working on advanced technology nodes below 5nm , such as 4nm, 3nm, or similar.
- Strong experience with TSMC process technologies .
- Strong understanding of:
- Setup and hold analysis
- Clock analysis and clock tree concepts
- Timing constraints
- SDC
- PVT corners
- OCV / AOCV / POCV
- MCMM analysis
- Signal integrity / crosstalk
- Timing ECOs
- Hands-on experience with Synopsys and/or Cadence EDA tools .
Preferred Tools
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