The Senior / Principal FPGA engineer would be responsible for design and development of FPGA designs using VHDL and verifying designs using VHDL or System Verilog.
Job Responsibilities
Creating innovative and robust VHDL-based designs
Documenting and recording deliverables
Verifying FPGA designs
Ensuring configuration management/keeping designs under revision control
Providing progress reports
Mandatory Skills & Qualifications
At least 5 years’ experience developing FPGA using VHDL or Verilog
Experienced with Mentor Graphics FPGA development tools including HDL Designer, ModelSim / Questa and Precision
Familiar with Xilinx / Intel (Altera) / Microsemi (Actel) design flows (ISE, Vivado, Quartus) and third‑party synthesis tools
Experience specifying timing and area constraints for efficient FPGA Placement and Routing
Independent verification using VHDL
Experience with FPGA requirements capture and requirements management tools
Good understanding of FPGA version control and revision control software
Experience making technical decisions and mitigating technical risk for FPGA design activities
Ability to coordinate day‑to‑day technical activities, liaising closely with the Project Engineering Lead / Lead FPGA engineer & other disciplines
Excellent communication (oral & written) & interpersonal skills
Ability to analyse system and/or hardware level requirements and derive detailed FPGA requirements
Debugging FPGA designs and supporting integration & verification at hardware and system level
Experience with high‑speed serial protocols and implementations
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