Senior Verification Engineer

Overview

In this role you will verify complex digital IP and modem subsystems for ASIC and FPGA implementations, ensuring functional and performance targets are met. You will build and maintain SystemVerilog/UVM environments, drive coverage and automation, and collaborate with RTL, architecture, and CI teams through tape-out. You’ll apply AI-assisted approaches to boost productivity while preserving quality and mentor junior engineers. The opportunity sits at the forefront of next-generation wireless and satellite communications, shaping high-performance digital design.

Responsibilities

• Develop verification plans from architecture and design specs
• Create and maintain SystemVerilog/UVM verification environments
• Build testbenches, assertions, scoreboards, and coverage models
• Perform directed and constrained-random verification
• Drive coverage analysis and closure
• Debug RTL and verification issues
• Support IP/subsystem/system-level integration
• Contribute to regression, automation, and CI workflows
• Participate in design reviews and verification sign-off
• Mentor junior engineers
• Leverage AI-assisted methods to improve verification productivity while ensuring quality

Key requirements

• 3+ years of experience verifying digital ASIC and/or FPGA designs
• Strong SystemVerilog and UVM experience
• Good understanding of RTL design and digital hardware principles
• Experience with coverage-driven and assertion-based verification
• Strong debugging and problem-solving skills
• Linux experience and scripting in Python, Tcl and/or Bash
• Experience collaborating across RTL, architecture and verification teams
• Degree in Electronic Engineering, Computer Engineering or a related discipline

• collaboration
• mentoring
• problem-solving
• SystemVerilog
• UVM
• verification environments

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