Senior FPGA Engineer

Overview

In this role you will help deliver a multi-FPGA platform where throughput, latency and predictability are critical. You’ll work on architecture, optimisation and implementation of deeply pipelined RTL, balancing clock frequency with area and latency. You’ll collaborate with software engineers and system architects, guide junior engineers, and translate complex requirements into robust hardware designs. The environment is collaborative and fast-moving, inviting you to share ideas and refine systems. This position offers the chance to contribute to high-performance compute hardware at scale and be part of shaping how complex specs become reliable hardware.

Responsibilities

• Design and optimise deeply pipelined RTL for multi-FPGA platforms
• Push clock frequency while managing area and latency trade-offs
• Collaborate with software engineers and system architects
• Review and mentor junior engineers
• Translate product requirements into clear technical specifications
• Test, debug, and improve system-level behaviour
• Contribute to architecture, optimisation and implementation efforts

Key requirements

• Strong experience with modern FPGA platforms (AMD/Xilinx or Intel/Altera)
• RTL coding experience in VHDL, Verilog, or SystemVerilog
• Background in building or optimising large, complex FPGA or ASIC systems
• Experience with high-performance, low-latency or deeply pipelined architectures
• Proven ability to test, debug, and improve system-level behaviour
• Comfort translating product-level requirements into technical specifications
• Experience with SoC architectures, accelerator-based systems, or ASIC-style environments would be beneficial

• collaborative
• strong communication
• ability to challenge assumptions
• AMD/Xilinx or Intel/Altera FPGA platforms
• VHDL, Verilog, or SystemVerilog RTL
• deeply pipelined/high-performance architectures

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