Senior Verification Engineer

Overview

As a Verification Engineer in Cambridge, you will own IP and chip-level verification planning and execution, collaborating with design teams to define verification plans and build test benches. You’ll work on next-generation silicon platforms and embedded/edge computing technologies, enabling scalable performance for developers, educators, engineers, and hobbyists. You’ll tackle low-power and complex protocol verification, contributing to a high-impact ASIC roadmap. This role offers a strong culture and leadership-driven environment with meaningful growth potential.

Pay / Benefits

• fantastic compensation package
• non-monetary benefits

Responsibilities

• Own IP and chip-level verification planning and execution
• Create verification plans and develop test benches from scratch or with shared components
• Collaborate with design team to ensure verification coverage and quality
• Work on low-power verification and SoC verification concepts (memory caches, DMA, security)
• Contribute to Cadence simulation tool flow including gate-level simulations
• Develop functional coverage and SystemVerilog Assertions (SVA)
• Support embedded C verifications for Cortex-M MCUs

Key requirements

• Hands-on experience with at least three projects
• Experience creating test benches from scratch using SystemVerilog, Python, or UVM
• Experience writing embedded C for Cortex-M class MCUs
• Knowledge of at least one complex IP protocol (PCIe, HDMI, USB, SDIO, AMBA)
• Ability to write functional coverage and SVA
• Understanding of design/front-end processes
• Experience with low-power simulations
• SoC verification concepts (memory caches, DMA, security architecture like TrustZone)
• Experience with Cadence simulation tool flow including gate-level simulation
• Scripting languages: Bash, TCL, Make, YAML

• self-driven
• collaborative
• good communication
• SystemVerilog
• UVM
• Python

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