Principal Datapath Design Engineer

Overview

In this role, you apply silicon design expertise to develop high-performance arithmetic hardware for GPUs within the Datapath team. You will collaborate with design, verification and validation to explore architectures and deliver hardware solutions that balance power, performance and area. You’ll translate requirements across engineering groups and prototype architectures, while contributing to patentable research and knowledge sharing. The role offers the chance to influence next-generation graphics hardware and be part of a research-driven, impact-focused organization.

Responsibilities

• Collaborate with design, verification and validation teams to develop silicon solutions
• Design and optimize arithmetic hardware components with a mathematically focused team
• Provide technical leadership and ensure timely project execution
• Extract and crystallise requirements for arithmetic hardware blocks across the organisation
• Prototype and evaluate hardware architectures under varying power, performance and area constraints
• Prepare microarchitecture design specifications and execution plans aligned with project goals
• Produce patentable work in a research-focused environment
• Plan and schedule own work and educate others on datapath designs
• Foster learning through training, knowledge sharing and guidance for junior engineers

Key requirements

• Solid knowledge of digital IC design techniques and methodologies
• Hands-on RTL design experience using VHDL or SystemVerilog
• Experience with ASIC or FPGA design tools and environments
• Practical experience with mainline branching and CI using Git and Jenkins
• Ability to improve processes and communicate complex technical information clearly
• Strong problem-solving skills and the ability to work with others to achieve outcomes

• excellent communicator
• listener and collaborator
• curious and solutions-oriented
• RTL design with VHDL or SystemVerilog
• ASIC or FPGA design tools and environments
• Git and Jenkins for CI/branching

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