Senior Verification Engineer

Overview

As a Senior Verification Engineer you will shape the verification strategy for complex FPGA designs within a fast-growing quantum technology company. You’ll own verification environments, driving methodology and best practices across the team, in a role that blends startup agility with the backing of a global organisation. You will work at the interface of FPGA development and quantum control systems, tackling challenging verification problems and contributing to scalable, automated workflows. This role offers ownership, impact and the chance to influence verification architecture in a cutting-edge domain.

Pay / Benefits

• competitive base salary
• RSUs
• bonus
• visa sponsorship and relocation support for engineers already in the UK

Responsibilities

• Architect, develop and maintain advanced UVM/SystemVerilog verification environments for complex FPGA designs
• Define and execute comprehensive verification plans
• Develop constrained-random test environments and drive functional and code coverage closure
• Collaborate with RTL/FPGA design engineers to debug failures and improve design quality
• Develop and maintain automated regression environments
• Support CI and verification workflows throughout the FPGA development lifecycle
• Help define and drive verification methodology and best practices across the FPGA team

Key requirements

• Strong SystemVerilog and UVM experience
• Experience architecting and developing verification environments
• Constrained-random and coverage-driven verification experience
• Verification planning and requirements gathering
• Python for scripting and test automation
• Strong debugging and problem-solving skills
• Experience working closely with RTL and/or FPGA design teams

• ownership and autonomy
• problem-solving
• collaboration
• SystemVerilog
• UVM
• constrained-random verification

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