Senior CPU Design Verification Engineer

Overview

In this role you will contribute to developing custom silicon solutions powering Client’s consumer products. You’ll work within a Research and Development team to build verification components, drive closure, and expose bugs through constrained-random testing and system-level validation. You’ll collaborate with design and verification engineers to verify digital RTL blocks and guide the full verification life cycle toward successful tape-out. This position offers the chance to influence high-performance hardware in a scale-driven AI infrastructure context.

Responsibilities

• Plan verification by interpreting design specs and identifying key scenarios
• Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and formal tools
• Define coverage measures for corner-cases and track progress
• Debug tests with design engineers to ensure functional correctness
• Close coverage gaps to demonstrate tape-out readiness

Key requirements

• Bachelor’s degree in electrical engineering or equivalent practical experience
• 8 years of experience in creating and using verification components and environments in standard verification methodology
• Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs

• collaboration
• problem-solving
• attention to detail
• SystemVerilog
• UVM
• SystemVerilog Assertions (SVA)

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