Senior Digital ASIC Design Engineer

An innovative semiconductor startup developing advanced ASIC technology for next generation medical and neurotechnology applications is looking for a Senior Digital ASIC Design Engineer. Their work combines ultra low power digital design with analogue and mixed signal technology, creating highly integrated solutions for demanding applications.

They are looking for a Senior Digital Design Engineer to take ownership of the front end digital development of their ASICs. This is a hands on role covering architecture, RTL design, verification and supporting the design through to silicon.

As a Senior Digital Design Engineer, you will:

• Own the architecture and RTL development of digital control, communication and power management functionality
• Develop clean, synthesizable Verilog/SystemVerilog for low power mixed signal ASICs
• Build and maintain SystemVerilog verification environments, including assertions, coverage and self checking testbenches
• Work closely with analogue and system engineers to define interfaces, registers, clocks and calibration functionality
• Take designs through lint, CDC/RDC, synthesis and timing analysis, working closely with Physical Design where required
• Support FPGA based prototyping, pre silicon validation and eventual silicon bring up
• Contribute to design reviews, technical documentation and verification planning

Required Experience

• Strong commercial experience in digital ASIC design and RTL development
• Hands on experience with Verilog and/or SystemVerilog
• Experience taking digital designs from specification or architecture through RTL development and synthesis
• Good understanding of digital verification, including testbenches, assertions and functional coverage
• Experience with common front end quality checks such as lint, CDC/RDC and timing constraints
• Experience working on mixed signal chips is highly desirable

The Senior Digital Design Engineer will suit someone who enjoys technical ownership and working across the ASIC development flow rather than being limited to a single stage of the process.

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