SerDes Architecture and Modelling Engineer

Overview

In this role you drive research and development of new SerDes concepts for high-speed serial links within a fast-growing semiconductor company. You will build system-level models to explore architectures, develop signal-processing algorithms, and evaluate their impact on link performance. You’ll translate research ideas into practical transceiver architectures alongside architects and IC designers. Expect a strong emphasis on innovation, validation against simulations and measurements, and cross-functional collaboration to shape next-generation solutions.

Pay / Benefits

• visa sponsorship
• relocation assistance

Responsibilities

• Research and develop new high-speed SerDes concepts
• Build system-level models to compare, optimise architectures
• Develop signal processing algorithms and assess impact on link performance
• Model communication systems using MATLAB, Python or C++
• Collaborate with architects and IC designers to translate concepts into architectures
• Analyse system limitations including SI, noise, power, clock recovery
• Define link budgets and block-level specifications from requirements
• Support analog, digital and verification teams throughout development

Key requirements

• Experience with system-level modelling of communication systems or SerDes technologies
• Understanding of signal integrity, channel behaviour, noise, jitter, equalisation, and link-performance analysis
• Ability to translate requirements into block-level specifications
• Ability to collaborate with multiple teams to validate models against simulations or measurements and maintain tested modelling software

• Collaborative mindset across cross-functional teams
• Strong communication of complex concepts
• Problem-solving and analytical thinking
• MATLAB
• Python
• C++

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