AMS

Job Title: AMS

Job ID: 89376

Location: Greater London, United Kingdom

What you will be doing:

• Own the verification strategy and test plan for our mixed-signal subsystems, from block level through subsystem and top-level integration.
• Define the modeling approach and fidelity tiers - decide what gets a real-number model, what needs Verilog-AMS, and where transistor-level co-sim is required - and document the accuracy/runtime trade-offs.
• Develop and validate analog behavioral models against transistor-level references, owning the model-vs-schematic equivalence checks that keep the abstraction honest.
• Build self-checking testbenches and reusable verification components for analog/digital interactions: CDR lock, adaptation and calibration loop convergence, mode and power-state transitions, clock dividers, deserializers, and clock-domain crossings.
• Drive AMS co-simulation flows (Spice/FastSpice coupled with digital simulators) and own their setup, performance, and runtime trade-offs.
• Define functional coverage and assertions that target analog corner behavior - saturation, overflow, polarity, loop stability, settling - not just digital state.
• Debug and root-cause failures across the analog/digital boundary, including discrepancies between behavioral and transistor-level results, and drive them to closure.
• Partner with analog and DSP designers to review specs, pin down interface contracts, and translate analog intent into checkable models, assertions, and tests.
• Own block- and subsystem-level verification sign-off for tape-out, including coverage closure and a clear statement of what AMS did and did not verify (functional vs. performance).
• Build and maintain regression infrastructure and flow automation, and improve AMS simulation throughput.
• Contribute to silicon bring-up and lab correlation, feeding measured behavior back into model validation.

What you must have:

• BS/MS in Electrical Engineering or related field, with 5+ years of analog/mixed-signal verification experience on complex SoCs or mixed-signal IP.
• Hands-on expertise with AMS modeling and verification: Verilog-AMS and real-number modeling (SystemVerilog real / wreal), and analog-digital co-simulation flows (e.g., Spectre AMS, FastSpice coupled with a digital simulator).
• Proficiency in SystemVerilog, with solid assertion-based verification skills and the ability to architect self-checking testbenches and reusable verification components.
• Demonstrated ability to model analog blocks at the appropriate level of abstraction and to validate those models against transistor-level references.
• Strong debug skills across the analog/digital boundary, with a structured approach to test planning, functional coverage, and closure.
• Comfort reading analog schematics and specifications and collaborating directly with analog and DSP designers.

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